Changfeng—a data center CPU built for the AI era. Based on an independently developed RISC-V core, Changfeng delivers end-to-end, high-performance design from microarchitecture through to the complete chip. It provides AI Agents with an independently controllable, future-ready computing foundation.
Complex Task Planning · Automated Tool Calling · Multi-Agent Sandbox Isolation · Long-Context RAG Retrieval
Microservice Scheduling · Distributed Databases · Containers and Virtualization · High-Concurrency Traffic Spikes
Multi-Tenant Hard Isolation · Domestic IT Substitution · High-Reliability RAS · Side-Channel Security Protection
In the Agent era, CPU workloads bring new computing challenges in latency, bandwidth, isolation, and IO. With a new microarchitecture and chip design, Changfeng CPU directly addresses the four key challenges limiting Agent computing power.
Addresses cache thrashing and multicore resource contention in the multi-step loops of Agent serial state machines. Delivers stable, predictable deterministic latency at every step, keeping the entire task chain running efficiently and reliably.
CPU bus and latency optimization. System Cache automatically detects and routes different workloads, combined with memory access stream shaping when writing back to DRAM. Mitigates resource conflicts between low-latency Agent workloads and high-bandwidth AI inference workloads, improving bandwidth utilization under mixed workloads.
Eliminates the resource contention and information security risks associated with dynamic sharing in traditional SMT. Provides hardware-level resource partitioning and isolation to support large-scale concurrent multi-agent workloads and ensure absolute multi-tenant data security.
Higher-bandwidth inter-chip interconnects and more efficient IO processing enable closer CPU-GPU memory coordination, reducing the performance losses caused by frequent data exchanges.
Hengyi Era RISC-V Ecosystem
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